One example of a PoDL system is referred to as a Class 14 system, where the wires between the PSE and PD can be 14 AWG (American Wire Gauge) and about 1000 meters in length. The IEEE specifies that the PSE must supply a minimum voltage of 50 VDC across the wires and supply a minimum power of 30 W. The maximum power that can be drawn by the PD is 20 W. Therefore, there is the assumption that the resistance of the wires (including all components in the power path between the PSE and PD) results in a loss of 10 W. This equates to a typical wire resistance of about 25 ohms.
However, if the wires used have a much lower resistance, such as if the wires are relatively short or a thicker gauge, there may be an actual power loss in the wires of, for example, only 1 W. Therefore, the PD can actually draw as high as 9 W more than the IEEE standard of 20 W (an almost 45% increase) without increasing the PSE power budget.
So, there is a benefit in knowing the actual wire resistance between the PSE and the PD if it is desired to maximize the allowable power drawn by the PD or have a more accurate PSE power budget. Knowing the actual wire resistance (and voltage drop) is also beneficial in systems where it is desired to deliver a precise voltage at the PD, which may obviate the need for a voltage regulator at the PD. Other benefits exist in knowing the actual wire resistance.
Two known techniques for approximately measuring the wire resistance between the PSE and PD are shown in FIGS. 1 and 2.
In FIG. 1, a PSE 10 supplies DC power to a PD 12 via the same wires 14 and 16 used to conduct Ethernet differential data. The PD load 18 receives the DC voltage at its pins P2 and P3 and may be any type of load, which includes logic circuitry. A blocking diode 19 ensures the voltage is the correct polarity and helps prevent reverse discharge of the charge storage capacitor 32. The supplied power also powers the PD's PHY 20, although the PHY 20 DC voltage input terminals are not shown for simplicity.
The PHY 20 outputs differential data and receives differential data via AC-coupling capacitors 22 and 24 coupled to wires 14 and 16 of a twisted wire pair. The PHY 20, in this example, represents the physical layer in the OSI model (Open Systems Interconnection model) and is a transceiver that typically includes signal conditioning and decoding circuitry for presenting bits to the next stage. The term PHY is well-known. The PHY 20 is typically an integrated circuit. A digital processor (not shown) is coupled to the PHY 20 for processing the data.
The PSE 10 has a similar PHY 26 and AC-coupling capacitors 28 and 30.
The PD 12 includes a capacitor 32 across the PD load 18 for smoothing the voltage across the PD load 18. The capacitor 32 may also provide charge storage for a downstream DC-DC converter. The converter would then convert the incoming voltage to a regulated voltage for another portion of the PD load.
DC-coupling inductors L1-L4 pass the DC voltage and block the differential data signals.
One technique for measuring the overall resistance of the DC power path between the PSE 10 and PD 12 is as follows. Prior to the PSE 10 supplying full DC power to the PD 12, the PSE 10 applies a low current pulse of a known magnitude (e.g., 15 mA) to the wire 14 using a current source 38. The PD load 18 detects the pulse, via buffer 40 and pin P1, and temporarily closes the MOSFET M1 switch to effectively short the ends of the inductors L3 and L4 together.
A reverse-blocking diode 42 ensures that current does not flow through the MOSFET M1 body diode when the MOSFET M1 is off.
The PSE logic circuit 44 then measures the voltage across its pins 46 and 48 and uses the known value of the current pulse to determine the resistance of the DC power path, using Ohm's law, through all components in the current loop. A buffer 49 at the pin 46 is optional. By knowing the actual resistance of the DC power path, the power dissipated by the DC power path for any PD current can be determined, and the PSE power budget can be adjusted accordingly.
The PD 12 can also detect the voltage V1 by sensing the voltage across its pins P1 and P2, but the voltage includes the voltage drop across the inductors L3 and L4.
After the resistance testing routine, and any low power handshaking routines between the PSE 10 and the PD 12, a power switch 50 is closed to supply the full PSE voltage VPSE across the wires 14 and 16 to power the PD 12.
A MOSFET M2 in the PSE 10 can be used to provide a reset signal to the PD 12. This reset signal is also used in the Serial Communication and Classification Protocol (SCCP) as specified in the IEEE standards.
One drawback of this technique is that the full current by the current source 38 flows through the PD inductors L3 and L4. This results in voltage drops across the inductors L3 and L4 due to the DC resistance (DCR) of the coils. Therefore, this technique causes inaccuracy in the measured resistance of the wires 14 and 16.
Another technique is depicted in FIG. 2, where the resistance of the wires 14 and 16 is more accurately measured. In this technique, two additional pins, P4 and P5, are added to the PD load 54 to detect the voltage V2 on the line-side of the inductors L3 and L4 so the voltage drop across the inductors L3 and L4 does not affect the voltage measurement by the PD load 54.
The PD 12 may measure the voltage across the wires 14 and 16 using an analog-to-digital converter. The measured voltage is then transmitted, as an 8-bit code, back to the PSE 10. The PSE 10 then calculates the detected voltage across the wires and uses the known current pulse to calculate the resistance of the wires 14 and 16 using Ohm's law. Thus, the calculated resistance of the wires 14 and 16 using this technique is more accurate compared to using the technique of FIG. 1.
A drawback in the technique of FIG. 2 is that two extra pins P4 and P5 and their connections need to be added to measure the voltage across the wires 14 and 16 at the PD 12. This adds cost and complexity.
Accordingly, what is needed is a technique that more accurately measures the resistance of conductors between a PSE and a PD which does not require additional pins and connections in the PD.